1. Field of the Invention
This invention relates to a semiconductor integrated circuit device with multilayered wirings.
2. Description of the Related Art
Recently, it is noticed that a resistance change memory device succeeds to the conventional flash memory. In the resistance change memory, the resistance value is reversibly exchanged by applying voltage, current or heat, and one of states with the different resistance values is stored as data. This resistance change memory is suitable for miniaturizing the cell size, and for constituting a cross-point cell array. In addition, it is easy to stack cell arrays.
There have already been proposed some three dimensional (3-D) cell array structures of this kind of memory devices. For example, refer to JP-A-2005-522045 (PCT/JP2003/000155) and JP-A-2006-514393 (PCT/JP2003/003257).
In case the cell array is three-dimensionally stacked, a multilayered metal wiring structure is used. In this case, how to equalize the wiring properties in the respective layers becomes material. For example, there have been proposed multi-layer wiring technologies such as: to make the CR time constant of the multilayered wirings constant (refer to JP-A-2004-146812); and to reduce the pad capacitance of the multilayered wirings in consideration of the number of via-wirings of the respective layers (refer to JP-A-2006-313824).